The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Nearly every device must be smaller without degrading operational performance of the integrated circuitry. High packing density, low heat generation, and low power consumption, with good reliability must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the dimensions of metal structures interconnecting transistors, channels between contacts, and other device features within an integrated circuit are significantly reduced—significantly altering the physical and electrical properties of those features. Ongoing efforts to reduce transistor geometries give rise to a number previously unaddressed performance and design issues, particularly in specialized or high-performance designs. Consider, for example, a junction field effect transistor (JFET).
Conventional JFETs are often produced in bipolar semiconductor technologies. These JFETs offer some beneficial properties, such as low leakage current and high current capacity, suitable for certain applications (e.g., buffers). Unfortunately, though, conventional JFETs have certain structural and behavioral properties that limit their usefulness in high-performance applications (e.g., high frequency, high voltage). In comparison to MOSFETs, JFETs have relatively high current capacities but relatively low gain. As such, some efforts have been made to produce JFETs retaining their beneficial properties, while adding certain performance properties that approach those of MOSFETs. This has, correspondingly, resulted in attempts to implement JFET architectures in commercial, MOS-type, photolithographic process technologies—raising a number of new issues and concerns.
Generally, the junction region of a JFET (i.e., the region comprising the interface of the channel and gate structures) is determinative of most of that JFET's performance characteristics. This is the region where voltage across the channel, and an electric field (or fields) resulting therefrom, alter depletion of charge under the gate—thereby altering the current throughput of the JFET. Thus, altering the structure, dimension or configuration of a JFET junction region can significantly contribute to or detract from that JFET's performance.
Conventional JFET structures typically comprise a central channel region within a base substrate, having a gate disposed atop it—forming the junction region. Laterally, along a single plane, the channel is bounded, on its sides, by areas doped to form the source and drain regions. Contacts are formed atop the source, drain and gate features to form the functional transistor. The gate is used to apply voltage to the junction region—pinching off the junction region and thereby controlling the current throughput of the JFET.
Within the junction region, a certain amount of non-linear parasitic capacitance originates from the interface between the channel and the gate (i.e., the top side of the channel). This parasitic capacitance can degrade the frequency performance of the JFET. Additionally, a certain amount of non-linear parasitic capacitance originates from each of the interfaces between the channel and the source and drain (i.e., the channel sidewalls). These interfaces—in comparison with the channel/gate interface—do nothing to contribute to controlling junction region pinch off. They do, however, contribute a significant amount of additional capacitance, greatly increasing the non-linearity of the parasitic capacitance and further impairing the frequency performance of the JFET. This effect is even more extensive in designs that implement a backside gate.
Certain JFET designs, depending upon the semiconductor process technology utilized, can or do provide a second gate structure (i.e., a “backside gate”) disposed along the bottom surface of the channel. Where such a structure is present, the non-linear parasitic capacitance is increased even further—decreasing the JFET's frequency performance. In order for a backside gate structure to contribute to controlling junction field effects, a contact must be made for it. This translates to patterning, routing, or otherwise producing a contact on the backside of the substrate. In most commercial applications, however, this is extremely impractical due to the cost and process overhead involved. Thus, the presence of a backside gate typically adds nothing to the control of junction field effects while further degrading the frequency performance of the JFET.
Theoretically, these detrimental capacitance effects could be diminished if the length of the channel was reduced significantly. Unfortunately, most conventional fabrication processes (e.g., lithography) are limited in their ability to reliably produce transistor features of extremely small dimension. Even where the ability to produce extremely fine processing tool features (e.g., mask dimensions) might exist, the ability to accurately predict and tightly control inherent processing material effects (e.g., diffusive spreading) often does not. For example, assume that a gate mask having a length dimension of 0.3 μm can be successfully produced—to be used in implanting a device feature intended to have a gate length dimension of 0.3 μm. Implantation of a dopant through the mask may nonetheless yield a device feature having a length dimension of 0.4 μm, 0.5 μm or larger—depending upon the inherent diffusivity of the dopant material during implant. Aside from such production difficulties, an extremely fine channel structure would cause other performance problems—particularly with respect to frequency performance. A gate contact to an extremely narrow channel would have extremely high resistance that would, consequently, degrade the frequency response of the transistor. Thus, in conventional processes, the ability to limit detrimental capacitance effects through channel length reduction is of little practical value.
As a result, there is a need for a system that provides for the design and production of high performance JFET structures—capable of high current throughput at high voltages and high frequencies—using commercially viable semiconductor process technologies in an easy, efficient and cost-effective manner.